High-speed input/output (IO) circuits (e.g., those that support a double data rate, “DDR”) use both the rising edge and the falling edge of a clock signal (or simply, clock) to sample data. If the clock does not have a good duty cycle, the rising edge and the falling edge of the clock cannot be properly aligned to sample data at the same time. The purpose of “receive clock duty cycle correction” is to properly align both the rising and falling edges of a clock with the data that is sampled.
Conventional IO circuits use analog detectors to perform receive clock duty cycle correction. These analog detectors typically include a differential amplifier (e.g., a front-end differential amplifier) connected with a differential clock. The output of the amplifier may be connected to an analog integrator (e.g., using a capacitor). These analog circuits typically consume a large die area. In addition, they are typically “always on” because their long settling time prohibits frequent power management of the clock distribution, which may consume a fair amount of power.